/* SPDX-License-Identifier: GPL-2.0 */
/*
 *------------------------------------------------------------------------------
 * @File      :    mi_ax.h
 * @Date      :    2021-3-16
 * @Author    :    lomboswer <lomboswer@lombotech.com>
 * @Brief     :    Media Interface for MDP(Media Development Platform).
 *
 * Copyright (C) 2020-2021, LomboTech Co.Ltd. All rights reserved.
 *------------------------------------------------------------------------------
 */
#ifndef __AX_H__
#define __AX_H__

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */

#ifdef CONFIG_ARCH_LOMBO_N7V7
	#define INITIAL_BOOT_CTRL_CHECK
	#define VX_CMDQ
	// #define FREQ_ACCURATE_MODE
	#define CMDNUM_REG_SHIFT 2
	// #define CHANGE_FREQ_BY_COOL_STATE
	// #define CHANGE_FREQ_RATIO_BY_COOL_STATE
	#define CHANGE_BW_BY_COOL_STATE
	#define BWLMT_TIMEWIN 6800
	#ifdef CONFIG_ARCH_LOMBO_N7V7_FPGA
		#define WORKING_IN_FPGA
	#endif
#endif

#ifdef CONFIG_ARCH_LOMBO_N7V5
	#define FREQ_ACCURATE_MODE
	#define CMDNUM_REG_SHIFT 6
	// #define CHANGE_FREQ_BY_COOL_STATE
	#define CHANGE_FREQ_RATIO_BY_COOL_STATE
	#define CHANGE_BW_BY_COOL_STATE
	#define BWLMT_TIMEWIN 5100
#endif

typedef struct eiAXNU_DBG_PERF_CNT_S {
	unsigned int mtiks;
	unsigned int mrbw;
	unsigned int mwbw;
} AXNU_DBG_PERF_CNT_S;

typedef struct eiAXNU_STAT_INFO_S {
	AXNU_DBG_PERF_CNT_S mstat;
	unsigned int mboxes;
	int status;
} AXNU_STAT_INFO_S;

typedef struct eiAXNU_CTL_S {
	unsigned int mFstCmdLen;
	unsigned int mCmdNum;
	unsigned int mCmdInt[4];
	unsigned int mCmdPAUS[4];
	unsigned int mISREn;
	unsigned int mCmdAddr;
	unsigned int mInputAddr;
	unsigned int mInternalAddr;
	unsigned int mOutputAddr;
	unsigned int mOcmEn;
	unsigned int mOcmAddr;
	unsigned int mWarpInAlign64;
} AXNU_CTL_S;

typedef struct eiAXNU_STATUS_OUT_S {
	int err_no;
	unsigned int mCmdInt[4];
} AXNU_STATUS_OUT_S;

typedef struct eiAXNU_PAUSE_FLAG_S {
	unsigned int mCmdPAUS[4];
} AXNU_PAUSE_FLAG_S;

typedef struct eiAX_REG_S {
	unsigned int reg_addr;
	unsigned int reg_val;
} AX_REG_S;

#ifdef VX_CMDQ
typedef struct eiAXVU_TASK_CTL_S {
	unsigned int mFstCmdLen;
	unsigned int mCmdNum;
	unsigned int mTaskInt;
	unsigned int mCmdAddr;
	void *mRes;  /* reserved for future use */
} AXVU_TASK_CTL_S;

typedef struct eiAXVU_CTL_S {
	unsigned int mTaskNum;
	AXVU_TASK_CTL_S mTaskCtl[8];
	unsigned int mOcmEn;
	unsigned int mOcmAddr;
	unsigned long long mAddrOfs; /* Extension address for 4GB sdram */
	void *mRes;  /* reserved for future use */
} AXVU_CTL_S;
#endif

typedef struct eiAXVU_DBG_PERF_CNT_S {
	unsigned int mtiks;
	unsigned int mrbw;
	unsigned int mwbw;
} AXVU_DBG_PERF_CNT_S;

typedef struct eiAXVU_STAT_INFO_S {
	AXVU_DBG_PERF_CNT_S mstat;
} AXVU_STAT_INFO_S;

#ifndef VX_CMDQ
typedef struct eiAXVU_RECT_S {
	int x;
	int y;
	int w;
	int h;
} AXVU_RECT_S;

typedef struct eiAXVU_RSZ_CFG_S {
	int iw;
	int ih;

	int oft_x;
	int oft_y;
	int crop_w;
	int crop_h;

	int yuv_limit_range;//1: limit 601, 0: full 601
	int istride;
	int fmt_in;
	int bw_in; // 16bit-gray, 8bit-rgb
	int bw_out;// 16bit-rgb, 8bit-rgb
	unsigned int phyaddrin;
	unsigned int phyaddrin_uv;
	unsigned int phyaddr2rd;
	AXVU_RECT_S hist_rect;
	int in_align_byte;
	int fmt_out;
	int ddr_type;

	int ow;
	int oh;
	int dst_stride;
	unsigned int phyaddrout;//TBD unsigned long long
	unsigned int phyaddrout_uv;//TBD unsigned long long
	unsigned int phyaddrhist;
	int merge_mode;
	int hist_en;
} AXVU_RSZ_CFG_S;

typedef struct eiAXVU_MBG_CFG_S {
	int iw;
	int ih;

	int cp_en;
	int cp_cnt;
	int pool_w;
	int pool_h;
	int thr_en;
	int thr;
	int alpha;
	int lstride;
	int reset_flg;//scene change
	int msk_thr;
	unsigned int phyaddrin;
	unsigned int phyaddrin_bg;
	unsigned int phyaddrout_bg;
	unsigned int phyaddrout_msk;
	unsigned int phyaddr_cp;
} AXVU_MBG_CFG_S;


typedef struct eiAXVU_PYM_CFG_S {
	int iw;
	int ih;
	int istride;
	int fmt_in;
	unsigned int phyaddrin;
	unsigned int phyaddrin_uv;
	int pym_layer;
	int fmt_out;
	int ow[8];
	int oh[8];
	unsigned int phyaddrout;
} AXVU_PYM_CFG_S;
#endif

int MI_AXNU_Init(void);
int MI_AXNU_Exit(int s32AxnuFd);
int MI_AXNU_SetFreq(int s32AxnuFd, unsigned int u32Freq);
int MI_AXNU_SetNormalFreq(int s32AxnuFd, unsigned int u32Freq);
int MI_AXNU_GetFreq(int s32AxnuFd, unsigned int *u32Freq);
int MI_AXNU_GetNormalFreq(int s32AxnuFd, unsigned int *u32Freq);
int MI_AXNU_Run(int s32AxnuFd, AXNU_CTL_S *pstAxnuCtrl);
int MI_AXNU_Query(int s32AxnuFd);

int MI_AXVU_Init(void);
int MI_AXVU_Exit(int s32AxvuFd);
int MI_AXVU_SetFreq(int s32AxvuFd, unsigned int s32Freq);
int MI_AXVU_GetFreq(int s32AxvuFd, unsigned int *s32Freq);
#ifdef VX_CMDQ
int MI_AXVU_Run(int s32AxvuFd, AXVU_CTL_S * pstAxnuCtrl);
#else
int MI_AXVU_MBG_RUN(int s32AxvuFd, AXVU_MBG_CFG_S *pstAxvuMbgCfgs);
int MI_AXVU_RSZ_RUN(int s32AxvuFd, AXVU_RSZ_CFG_S *pstAxvuRszCfgs);
#endif

#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */

#endif
